IC's, also known as chips, may be made more powerful if the number of devices on each chip can be increased. Increasing the level of device integration on a chip is useful only if the performance characteristics of the devices scale as the physical scale of the devices themselves is reduced. To the extent this is true, chips may be made using very large scale integration (VLSI) techniques preserving the important performance characteristics of the devices included in the network.
Where the device characteristics are faithfully preserved the increased device density leads to improved performance. However, the improvement in chip performance may be mitigated by the reality that certain other device characteristics do not scale with the physical dimensions of the chip.
Among these non-scaling factors is the ability of the chip- its input/output pad, gate oxide and dielectric substrate material- to withstand high energy ESD events during shipping and handling. Scaling down of the device size necessarily results in the use of thinner gate oxides and shallower junctions beneath the oxide. In addition, the radius of curvature of the junction may decrease as well. The smaller radius of curvature may result in increased electrostatic potentials being generated between the oxide and the substrate during ESD stress. As a consequence, the electrostatic potential does not scale with the junction depth and the oxide thickness.
Increasing integration, therefore, increases chip vulnerability to ESD failure. Wafer probing and wire bonding leave the I/O pad surface punched through with holes and create microscopic cracks in the dielectric substrate itself. When the chip experiences a high voltage ESD, these holes and micro cracks may generate strong electric fields. If the ESD energy cannot be quickly dissipated through the power lines or the substrate, the oxide beneath the pad may rupture. The rupture of the pad may provide leakage paths from the pad to the substrate hastening failure of the chip.
Since ESD can damage an IC during handling, it is conventional to connect an ESD protection device to the I/O pad (such as I/O pad 10 of FIG. 1). Sometimes a polysilicon (poly) resistor 20 is connected between the I/O pad 10 and the ESD protection device 30 as shown in FIG. 1. Typically, the poly resistor 20 is placed on top of an oxide layer which grows on the semiconductor substrate. For the input pad, this resistor can limit the input injection current when the input voltage is lower than the ground potential or higher than V.sub.cc, the external power supply voltage. For the output, the resistor may be used for resistance matching. However, during ESD testing the oxide may become damaged precisely because of the presence of the poly resistor.
Consequently, it would be desirable to reduce the electrostatic potential across the oxide adjacent
PATENT the poly resistor. It is the object of this invention to reduce this electrostatic potential without eliminating the otherwise useful poly resistor from the ESD protection network. This is accomplished by connecting a substrate well to a fixed potential during normal operation of the chip. However, when the chip is not in normal operation or is being handled, the substrate well is allowed to float.